DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 106

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
Allocating different page registers for read and write
access allows the architecture to support data
movement between different pages in data memory.
This is accomplished by setting the DSRPAG register
value to the page from which you want to read, and
configuring the DSWPAG register to the page to which
it needs to be written. Data can also be moved from
different PSV to EDS pages, by configuring the
DSRPAG and DSWPAG registers to address PSV and
EDS space, respectively. The data can be moved
between pages by a single instruction.
When an EDS or PSV page overflow or underflow
occurs, EA<15> is cleared as a result of the register
indirect EA calculation. An overflow or underflow of the
EA in the EDS or PSV pages can occur at the page
boundaries when:
• The initial address prior to modification addresses
• The EA calculation uses pre- or post-modified
TABLE 4-61:
DS70657F-page 106
O,
Read
O,
Read
O,
Read
O,
Write
U,
Read
U,
Read
U,
Read
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1:
O/U,
R/W
an EDS or PSV page
register indirect addressing. However, this does
not include register offset addressing
2:
3:
4:
Operation
[++Wn]
[Wn++]
[--Wn]
[Wn--]
The register indirect address now addresses a location in the base data space (0x0000-0x8000).
An EDS access with DSxPAG = 0x000 will generate an address error trap.
Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate
an address error trap.
Pseudo-linear addressing is not supported for large offsets.
or
or
OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS, and PSV SPACE
BOUNDARIES
DSRPAG = 0x1FF
DSRPAG = 0x2FF
DSRPAG = 0x3FF
DSWPAG = 0x1FF
DSRPAG = 0x001
DSRPAG = 0x200
DSRPAG = 0x300
DSxPAG
Before
EA<15>
DS
1
1
1
1
1
1
1
EDS: Last page
PSV: Last lsw
page
PSV: Last MSB
page
EDS: Last page
PSV page
PSV: First lsw
page
PSV: First MSB
page
Description
Page
In general, when an overflow is detected, the DSxPAG
register is incremented, and the EA<15> bit is set to
keep the base address within the EDS or PSV window.
When an underflow is detected, the DSxPAG register is
decremented, and the EA<15> bit is set to keep the
base address within the EDS or PSV window. This
creates a linear EDS and PSV address space, but only
when using Register Indirect Addressing modes.
Exceptions to the operation described above arise
when entering and exiting the boundaries of page 0,
EDS, and PSV spaces.
overflow
boundaries.
In the following cases, when overflow or underflow
occurs, the EA<15> bit is set and the DSxPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
• Register indirect with register offset addressing
• Modulo Addressing
• Bit-reversed addressing
DSRPAG = 0x1FF
DSRPAG = 0x300
DSRPAG = 0x3FF
DSWPAG = 0x1FF
DSRPAG = 0x001
DSRPAG = 0x200
DSRPAG = 0x2FF
and
DSxPAG
underflow
 2011-2012 Microchip Technology Inc.
Table 4-61
EA<15>
After
scenarios
DS
0
1
0
0
0
0
1
lists the effects of
See Note 1
PSV: First MSB
page
See Note 1
See Note 1
See Note 1
See Note 1
PSV: Last lsw
page
Description
at
Page
different