DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 151

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

9.0
FIGURE 9-1:
 2011-2012 Microchip Technology Inc.
R
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
(2)
Note 1:
OSC1
OSC2
2: Some registers and associated bits
OSCILLATOR CONFIGURATION
2:
3:
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer
(DS70580) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Primary Oscillator
See
If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
The term F
ment, F
used with a doze ratio of 1:2 or lower.
POSCMD<1:0>
Oscillator
TUN<5:0>
Oscillator
Figure 9-2
FRC
LPRC
to
the
CY
OSCILLATOR SYSTEM DIAGRAM
and F
P
Section
refers to the clock source for all peripherals, while F
FRCCLK
for PLL and F
P
dsPIC33EPXXXGP50X,
are used interchangeably, except in the case of DOZE mode. F
S1
S3
POSCCLK
7.
÷ 16
VCO
“Oscillator”
families
details.
FRCDIV<2:0>
PLL
(1)
and
of
in
XTPLL, HSPLL,
ECPLL, FRCPLL
F
VCO (1)
Clock Fail
S7
XT, HS, EC
FRCDIV16
FRCDIVN
LPRC
FRC
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X oscillator system
provides:
• On-chip Phase-Locked Loop (PLL) to boost inter-
• On-the-fly clock switching between various clock
• Doze mode for system power savings
• Fail-Safe Clock Monitor (FSCM) that detects clock
• Configuration bits for clock source selection
A simplified diagram of the oscillator system is shown
in
nal operating frequency on select internal and
external oscillator sources
sources
failure and permits safe application recovery or
shutdown
Figure
CY
Clock Switch
NOSC<2:0> FNOSC<2:0>
refers to the clock source for the CPU. Throughout this docu-
S2
S1/S3
S7
S6
S0
S5
9-1.
Reference Clock Generation
POSCCLK
P
and F
Reset
F
÷ 2
OSC
CY
ROSEL RODIV<3:0>
DOZE<2:0>
will be different when DOZE mode is
÷ N
DS70657F-page 151
REFCLKO
WDT, PWRT,
F
F
F
FSCM
P
CY (3)
OSC
(3)
RPn