DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 226

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
16.1.2
On
PIC24EPXXXMC20X devices, write protection is
implemented for the IOCONx and FCLCONx registers.
The write protection feature prevents any inadvertent
writes to these registers. This protection feature can be
controlled by the PWMLOCK Configuration bit
(FOSCSEL<6>). The default state of the write
protection feature is enabled (PWMLOCK = 1). The
write protection feature can be disabled by configuring
PWMLOCK = 0.
EXAMPLE 16-1:
DS70657F-page 226
; FLT32 pin must be pulled low externally in order to clear and disable the fault
; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd,w10
mov #0x4321,w11
mov #0x0000,w0
mov w10, PWMKEY
mov w11, PWMKEY
mov w0,FCLCON1
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov #0xabcd,w10
mov #0x4321,w11
mov #0xF000,w0
mov w10, PWMKEY
mov w11, PWMKEY
mov w0,IOCON1
WRITE-PROTECTED REGISTERS
dsPIC33EPXXXMC20X/50X
PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; Load first unlock key to w10 register
; Load second unlock key to w11 register
; Load desired value of FCLCON1 register in w0
; Write first unlock key to PWMKEY register
; Write second unlock key to PWMKEY register
; Write desired value to FCLCON1 register
; Load first unlock key to w10 register
; Load second unlock key to w11 register
; Load desired value of IOCON1 register in w0
; Write first unlock key to PWMKEY register
; Write second unlock key to PWMKEY register
; Write desired value to IOCON1 register
and
To gain write access to these locked registers, the user
application must write two consecutive values of
(0xABCD and 0x4321) to the PWMKEY register to
perform the unlock operation. The write access to the
IOCONx or FCLCONx registers must be the next SFR
access following the unlock process. There can be no
other SFR accesses during the unlock process and
subsequent write access. To write to both the IOCONx
and
operations.
The correct unlocking sequence is described in
Example
FCLCONx
16-1.
 2011-2012 Microchip Technology Inc.
registers
requires
two
unlock