DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 367

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 25-6:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-7
bit 6-4
bit 3
bit 2-0
Note 1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
U-0
U-0
—
—
2:
3:
4:
See the Type C Timer Block Diagram
See the Type B Timer Block Diagram
See the PWM Module Register Interconnect Diagram
See the Oscillator System Diagram
Unimplemented: Read as ‘0’
CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = T5CLK
110 = T4CLK
101 = T3CLK
100 = T2CLK
011 = Reserved
010 = SYNCO1
001 = F
000 = F
CFLTREN: Comparator Filter Enable bit
1 = Digital filter enabled
0 = Digital filter disabled
CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
R/W-0
U-0
—
CMxFLTR: COMPARATOR FILTER CONTROL REGISTER
OSC
P
(4)
(4)
(1)
(2)
(1)
(2)
CFSEL<2:0>
W = Writable bit
‘1’ = Bit is set
(3)
R/W-0
U-0
—
(Figure
R/W-0
(Figure
(Figure
U-0
—
9-1).
13-1).
13-2).
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CFLTREN
R/W-0
U-0
—
(Figure
16-2).
R/W-0
U-0
—
CFDIV<2:0>
x = Bit is unknown
R/W-0
U-0
—
DS70657F-page 367
R/W-0
I-0
—
bit 8
bit 0