DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 172

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
11.1.1
In addition to the PORT, LAT and TRIS registers for
data control, port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs other than V
resistors. The maximum open-drain voltage allowed
on any pin is the same as the maximum V
specification for that particular pin.
See the
5V-tolerant pins and
V
11.2
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs or outputs must have their corresponding
ANSEL and TRIS bits set. In order to use port pins for
I/O functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
Pins with analog functions affected by the ANSELx
registers are listed with a buffer type of Analog in the
Pinout I/O Descriptions (see
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (V
by an analog peripheral, such as the ADC module or
Comparator module.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
11.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP, as shown in
DS70657F-page 172
IH
specification for each pin.
Configuring Analog and Digital
Port Pins
“Pin Diagrams”
OPEN-DRAIN CONFIGURATION
I/O PORT WRITE/READ TIMING
Table 30-10
DD
by using external pull-up
section for the available
Table
Example
OH
or V
1-1).
for the maximum
OL
11-1.
) is converted
IH
11.3
The input change notification function of the I/O ports
allows devices to generate interrupt requests to the
processor in response to a change-of-state on selected
input pins. This feature can detect input change-of-
states even in Sleep mode, when the clocks are
disabled. Every I/O port pin can be selected (enabled)
for generating an interrupt request on a change-of-
state.
Three control registers are associated with the CN
functionality of each I/O port. The CNENx registers
contain the CN interrupt enable control bits for each of
the input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups and pull-
downs act as a current source or sink source
connected to the pin, and eliminate the need for
external resistors when push-button or keypad
devices are connected. The pull-ups and pull-downs
are enabled separately using the CNPUx and the
CNPDx registers, which contain the control bits for
each of the pins. Setting any of the control bits
enables the weak pull-ups and/or pull-downs for the
corresponding pins.
EXAMPLE 11-1:
MOV
MOV
NOP
BTSS
Note:
0xFF00, W0
W0, TRISB
PORTB, #13
Input Change Notification
Pull-ups and pull-downs on change notifi-
cation pins should always be disabled
when the port pin is configured as a digital
output.
 2011-2012 Microchip Technology Inc.
PORT WRITE/READ
EXAMPLE
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0>
; as outputs
; Delay 1 cycle
; Next Instruction