DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 369

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

26.0
FIGURE 26-1:
FIGURE 26-2:
 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
Shift Buffer
Data
2: Some registers and associated bits
PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
2: Polynomial length n is determined by ([PLEN<4:0>] + 1).
2 * F
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “Program-
mable
(CRC)” (DS70346) of the “dsPIC33E/
PIC24E
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
P
Shift Clock
the
Cyclic
CRC BLOCK DIAGRAM
CRC SHIFT ENGINE DETAIL
Family Reference Manual”,
dsPIC33EPXXXGP50X,
Redundancy
Bit 0
Read/Write Bus
CRCWDATH
CRCDATH
families
(4x32, 8x16 or 16x8)
CRC Shift Engine
X(1)
Variable FIFO
Shift Buffer
Check
(1)
CRCWDATH
0
and
of
in
1
Bit 1
CRCWDATL
CRCDATL
LENDIAN
The programmable CRC generator offers the following
features:
• User-programmable (up to 32nd order)
• Interrupt output
• Data FIFO
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable Interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in
engine is shown in
polynomial CRC equation
up to 32 bits
X(2)
Shift Complete Event
FIFO Empty Event
(1)
Figure
Bit 2
26-1. A simple version of the CRC shift
Figure
CRCWDATL
CRCISEL
26-2.
1
0
X(n)
Set CRCIF
(1)
DS70657F-page 369
Bit n
(2)