DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 342

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
REGISTER 24-6:
REGISTER 24-7:
DS70657F-page 342
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
R/W-0
R/W-0
R/W-0
R/W-0
2:
A base step delay of one PTG clock is added to any value written to the PTGSDLIM register (Step
Delay = (PTGSDLIM) + 1).
This register is read only when the PTG module is executing step commands (PTGEN = 1 and
PTGSTRT = 1).
This register is read only when the PTG module is executing step commands (PTGEN = 1 and
PTGSTRT = 1).
PTGSDLIM<15:0>: PTG Step Delay Limit Register bits
Holds a PTG Step Delay value representing the number of additional PTG clocks between the start of
a step command, and the completion of the step command.
PTGC0LIM<15:0>: PTG Counter 0 Limit Register bits
May be used to specify the loop count for the PTGJMPC0 step command, or as a limit register for the
general purpose counter 0.
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM: PTG STEP DELAY LIMIT REGISTER
PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM<15:8>
PTGC0LIM<15:8>
PTGSDLIM<7:0>
PTGC0LIM<7:0>
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1,2)
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0