DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 129

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

7.3
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
7.3.1
• Section 6. “Interrupts” (DS70600)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33E/PIC24E Family Reference
• Development Tools
7.4
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and PIC24EPXXXGP/MC20X devices implement the
following registers for the interrupt controller:
• INTCON1
• INTCON2
• INTCON3
• INTCON4
• INTTREG
7.4.1
Global interrupt control functions are controlled from
INTCON1, INTCON2, INTCON3 and INTCON4.
INTCON1 contains the Interrupt Nesting Disable bit
(NSTDIS) as well as the control and status flags for the
processor trap sources.
The INTCON2 register controls external interrupt
request signal behavior and also contains the General
Interrupt Enable bit (GIE).
INTCON3 contains the status flags for the DMA, and
DO stack overflow status trap sources.
The
generated hard trap status bit (SGHT).
 2011-2012 Microchip Technology Inc.
Note:
Manuals Sections
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
INTCON4
Interrupt Resources
Interrupt Control and Status
Registers
In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
KEY RESOURCES
INTCON1 THROUGH INTCON4
register
contains
the
software
7.4.2
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.4.3
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.4.4
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.4.5
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<7:0>) and Interrupt level bit (ILR<3:0>)
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
7.4.6
Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers refer to
Section 2. “CPU” (DS70359) in the “dsPIC33E/
PIC24E Family Reference Manual”.
• The CPU STATUS register, SR, contains the
• The CORCON register contains the IPL3 bit
All Interrupt registers are described in
through
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
software can change the current CPU priority
level by writing to the IPL bits.
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
Register 7-7
Table
IFSx
IECx
IPCx
INTTREG
STATUS/CONTROL REGISTERS
7-1. For example, the INT0 (External
in the following pages.
DS70657F-page 129
Register 7-3