C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 109

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201

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12.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs
found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the
sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 12.2 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to
0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well as
byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for
future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding
pages of the datasheet, as indicated in Table 12.3, for a detailed description of each register.
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
ACC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
D8
D0
C8
C0
B8
B0
A8
A0
F8
F0
E8
E0
98
90
88
80
(bit addressable)
ADC0CN
SMB0CN
PCA0CN
SPI0CN
T2CON
SCON0
TCON
ACC
PSW
0(8)
P3
P2
P1
P0
IP
IE
B
Address
Table 12.2. Special Function Register (SFR) Memory Map
0xBC
SMB0STA SMB0DAT SMB0ADR ADC0GTL ADC0GTH
0xC5
0xC4
0xBF
0xBE
0xE0
0xE8
OSCXCN
TMR3CN
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
SADEN0
SADDR0
REF0CN
EMI0TC
T4CON
PCA0H
SCON1
PCA0L
SBUF0
TMOD
XBR0
1(9)
SP
Table 12.3. Special Function Registers
Description
Accumulator
ADC0 Configuration
ADC0 Control
ADC0 Greater-Than High
ADC0 Greater-Than Low
ADC0 Data Word High
ADC0 Data Word Low
PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPH3 PCA0CPH4
PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4
TMR3RLL TMR3RLH
AMX0CF
ADC1CN
SPI0CFG
RCAP2L
OSCICN
DAC0L
SBUF1
XBR1
DPL
2(A)
TL0
AMX0SL
SADDR1
RCAP2H
SPI0DAT
ADC1CF
EMI0CF
DAC0H
XBR2
DPH
3(B)
TL1
Rev. 1.4
P0MDOUT P1MDOUT P2MDOUT P3MDOUT
DAC0CN
AMX1SL
ADC0CF
RCAP4L
TMR3L
ADC1
TH0
4(C)
TL4
TL2
P4†
P74OUT†
SPI0CKR
RCAP4H
P1MDIN
TMR3H
DAC1L
P3IF
5(D)
TH4
TH2
TH1
P5†
C8051F020/1/2/3
ADC0LTL ADC0LTH
SADEN1
CPT0CN
CKCON
DAC1H
ADC0L
FLSCL
EIP1
EIE1
page 49*, page 65**
page 50*, page 66**
page 53*, page 69**
page 53*, page 69**
page 51*, page 67**
page 51*, page 67**
6(E)
P7†
P6†
Page No.
page 115
DAC1CN
SMB0CR
WDTCN
RSTSRC
EMI0CN
CPT1CN
ADC0H
FLACL
PSCTL
PCON
EIE2
EIP2
7(F)
109

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