C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 266

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
24.1. Boundary Scan
The DR in the Boundary Scan path is an 134-bit shift register. The Boundary DR provides control and observability
of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands.
266
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
6, 8, 10, 12, 14, 16,
7, 9, 11, 13, 15, 17,
102, 104, 106, 108,
103, 105, 107, 109,
110, 112, 114, 116
22, 24, 26, 28, 30,
23, 25, 27, 29, 31,
38, 40, 42, 44, 46,
39, 41, 43, 45, 47,
54, 56, 58, 60, 62,
55, 57, 59, 61, 63,
70, 72, 74, 76, 78,
71, 73, 75, 77, 79,
86, 88, 90, 92, 94,
87, 89, 91, 93, 95,
111, 113, 115, 117
96, 98, 100
97, 99, 101
32, 34, 36
33, 35, 37
48, 50, 52
49, 51, 53
64, 66, 68
65, 67, 69
80, 82, 84
81, 83, 85
19, 21
18, 20
Bit
0
1
2
3
4
5
Action
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Table 24.1. Boundary Data Register Bit Definitions
Target
Reset Enable from MCU (C8051F021/3 devices)
Reset Enable to /RST pin (C8051F021/3 devices)
Reset input from /RST pin (C8051F021/3 devices)
Reset output to /RST pin (C8051F021/3 devices)
Reset Enable from MCU (C8051F020/2 devices)
Reset Enable to /RST pin (C8051F020/2 devices)
Reset input from /RST pin (C8051F020/2 devices)
Reset output to /RST pin (C8051F020/2 devices)
External Clock from XTAL1 pin
Not used
Weak pullup enable from MCU
Weak pullup enable to Port Pins
P0.n output enable from MCU (e.g. Bit6=P0.0, Bit8=P0.1, etc.)
P0.n output enable to pin (e.g. Bit6=P0.0oe, Bit8=P0.1oe, etc.)
P0.n input from pin (e.g. Bit7=P0.0, Bit9=P0.1, etc.)
P0.n output to pin (e.g. Bit7=P0.0, Bit9=P0.1, etc.)
P1.n output enable from MCU
P1.n output enable to pin
P1.n input from pin
P1.n output to pin
P2.n output enable from MCU
P2.n output enable to pin
P2.n input from pin
P2.n output to pin
P3.n output enable from MCU
P3.n output enable to pin
P3.n input from pin
P3.n output to pin
P4.n output enable from MCU
P4.n output enable to pin
P4.n input from pin
P4.n output to pin
P5.n output enable from MCU
P5.n output enable to pin
P5.n input from pin
P5.n output to pin
P6.n output enable from MCU
P6.n output enable to pin
P6.n input from pin
P6.n output to pin
Rev. 1.4

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