C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 86

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
86
Bit7:
Bits6-5:
Bits4-3:
Bits2-0:
DAC0EN
MSB
R/W
Bit7
MSB
DAC0EN: DAC0 Enable Bit.
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode.
1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational.
UNUSED. Read = 00b; Write = don’t care.
DAC0MD1-0: DAC0 Mode Bits.
00: DAC output updates occur on a write to DAC0H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
DAC0DF2-0: DAC0 Data Format Bits:
000:
001:
010:
011:
1xx:
MSB
R/W
Bit6
-
The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least
significant byte is in DAC0L.
The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least
significant 7-bits are in DAC0L[7:1].
The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least
significant 6-bits are in DAC0L[7:2].
The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least
significant 5-bits are in DAC0L[7:3].
The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least
significant 4-bits are in DAC0L[7:4].
MSB
DAC0H
DAC0H
DAC0H
DAC0H
DAC0H
Figure 8.4. DAC0CN: DAC0 Control Register
R/W
Bit5
MSB
-
DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000
R/W
Bit4
Rev. 1.4
R/W
Bit3
R/W
Bit2
LSB
R/W
Bit1
DAC0L
DAC0L
DAC0L
DAC0L
DAC0L
LSB
R/W
Bit0
LSB
LSB
SFR Address:
Reset Value
0xD4
LSB

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