C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 238
Manufacturer Part Number
IC 8051 MCU 64K FLASH 64TQFP
Silicon Laboratories Inc
Specifications of C8051F021-GQ
Program Memory Type
Program Memory Size
64KB (64K x 8)
Package / Case
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
A/D 8x8b, 8x12b; D/A 2x12b
-40°C ~ 85°C
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
8-ch x 8-bit or 8-ch x 12-bit
2-ch x 12-bit
No. Of I/o's
Ram Memory Size
No. Of Timers
No. Of Pwm Channels
Data Rom Size
A/d Bit Size
A/d Channels Available
Supply Voltage (max)
Supply Voltage (min)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
TF2: Timer 2 Overflow Flag.
Set by hardware when Timer 2 overflows. When the Timer 2 interrupt is enabled, setting this bit
causes the CPU to vector to the Timer 2 interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software. TF2 will not be set when RCLK0 and/or TCLK0 are
EXF2: Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the T2EX
input pin and EXEN2 is logic 1. When the Timer 2 interrupt is enabled, setting this bit causes the
CPU to vector to the Timer 2 Interrupt service routine. This bit is not automatically cleared by hard-
ware and must be cleared by software.
RCLK0: Receive Clock Flag for UART0.
Selects which timer is used for the UART0 receive clock in modes 1 or 3.
0: Timer 1 overflows used for receive clock.
1: Timer 2 overflows used for receive clock.
TCLK0: Transmit Clock Flag for UART0.
Selects which timer is used for the UART0 transmit clock in modes 1 or 3.
0: Timer 1 overflows used for transmit clock.
1: Timer 2 overflows used for transmit clock.
EXEN2: Timer 2 External Enable.
Enables high-to-low transitions on T2EX to trigger captures or reloads when Timer 2 is not operating
in Baud Rate Generator mode.
0: High-to-low transitions on T2EX ignored.
1: High-to-low transitions on T2EX cause a capture or reload.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2.
0: Timer 2 disabled.
1: Timer 2 enabled.
C/T2: Counter/Timer Select.
0: Timer Function: Timer 2 incremented by clock defined by T2M (CKCON.5).
1: Counter Function: Timer 2 incremented by high-to-low transitions on external input pin (T2).
CP/RL2: Capture/Reload Select.
This bit selects whether Timer 2 functions in capture or auto-reload mode. EXEN2 must be logic 1 for
high-to-low transitions on T2EX to be recognized and used to trigger captures or reloads. If RCLK0
or TCLK0 is set, this bit is ignored and Timer 2 will function in auto-reload mode.
0: Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1).
1: Capture on high-to-low transition at T2EX (EXEN2 = 1).
Figure 22.14. T2CON: Timer 2 Control Register