C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 210

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
20.2. Multiprocessor Communications
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors
by special use of the ninth data bit and the built-in UART0 address recognition hardware. A master processor begins
a transfer with an address byte to select one or more target slave devices. An address byte differs from a data byte in
that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
The UART0 address is configured via two SFRs: SADDR0 (Serial Address) and SADEN0 (Serial Address Enable).
SADEN0 sets the bit mask for the address held in SADDR0: bits set to logic 1 in SADEN0 correspond to bits in
SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0 correspond to “don’t
care” bits in SADDR0.
Setting the SM20 bit (SCON0.5) configures UART0 such that when a stop bit is received, UART0 will generate an
interrupt only if the ninth bit is logic 1 (RB80 = 1) and the received data byte matches the UART0 slave address. Fol-
lowing the received address interrupt, the slave should clear its SM20 bit to enable interrupts on the reception of the
following data byte(s). Once the entire message is received, the addressed slave should reset its SM20 bit to ignore all
transmissions until it receives the next address byte. While SM20 is logic 1, UART0 ignores all bytes that do not
match the UART0 address and include a ninth bit that is logic 1.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast address is the logi-
cal OR of registers SADDR0 and SADEN0, and ‘0’s of the result are treated as “don’t cares”. Typically a broadcast
address of 0xFF (hexadecimal) is acknowledged by all slaves, assuming “don’t care” bits as ‘1’s. The master proces-
sor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is
temporarily reversed to enable half-duplex transmission between the original master and slave(s).
210
UART0 Address = xxxx0101
SADDR0
SADEN0
RX
Example 1
Master
Device
Figure 20.7. UART Multi-Processor Mode Interconnect Diagram
TX
= 00110101
= 00001111
RX
Device
Slave
UART0 Address = 0011xx01
TX
SADDR0
SADEN0
Example 2
Rev. 1.4
RX
Device
Slave
= 00110101
= 11110011
TX
RX
Device
Slave
UART0 Address = 00xxxxxx
SADDR0
SADEN0
TX
Example 3
+5V
= 00110101
= 11000000

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