C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 18

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
18
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
MONEN
XTAL1
XTAL2
VREFD
VREF0
DGND
DGND
DGND
AGND
AGND
/RST
VREF
DAC1
DAC0
CP0+
CP0-
CP1+
CP1-
VDD
VDD
VDD
AV+
AV+
TCK
TMS
TDI
TDO
CP0
Analog Power
Digital Power
M
A
U
X
Oscillator
Oscillator
External
Monitor
Internal
Circuit
VDD
CP1
JTAG
Logic
(12-Bit)
(12-Bit)
VREF
DAC1
DAC0
SENSOR
TEMP
Prog
Gain
Boundary Scan
WDT
Debug HW
System
Clock
100ksps
(12-Bit)
Figure 1.1. C8051F020 Block Diagram
ADC
Reset
C
8
0
5
1
o
e
r
External Data Memory Bus
256 byte
64kbyte
SFR Bus
FLASH
4kbyte
RAM
RAM
Rev. 1.4
Timers 0,
Crossbar
Timer 3/
Port I/O
SPI Bus
Latches
UART0
UART1
SMBus
P0, P1,
Config.
P2, P3
Config.
1, 2, 4
PCA
RTC
Address Bus
Bus Control
Data Bus
ADC
500ksps
(8-Bit)
C
D
T
L
A
d
d
a
a
r
t
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
Prog
Gain
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
M
U
X
8:1
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
VREF1
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7

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