C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 75

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
7.
The ADC1 subsystem for the C8051F020/1/2/3 consists of an 8-channel, configurable analog multiplexer (AMUX1),
a programmable gain amplifier (PGA1), and a 500 ksps, 8-bit successive-approximation-register ADC with inte-
grated track-and-hold (see block diagram in Figure 7.1). The AMUX1, PGA1, and Data Conversion Modes, are all
configurable under software control via the Special Function Registers shown in Figure 7.1. The ADC1 subsystem
(8-bit ADC, track-and-hold and PGA) is enabled only when the AD1EN bit in the ADC1 Control register (ADC1CN)
is set to logic 1. The ADC1 subsystem is in low power shutdown when this bit is logic 0. The voltage reference used
by ADC1 is selected as described in
C8051F020/2 devices, or
devices.
7.1.
Eight ADC1 channels are available for measurement, as selected by the AMX1SL register (see Figure 7.5). The PGA
amplifies the ADC1 output signal by an amount determined by the states of the AMP1GN2-0 bits in the ADC1 Con-
figuration register, ADC1CF (Figure 7.4). The PGA can be software-programmed for gains of 0.5, 1, 2, or 4. Gain
defaults to 0.5 on reset.
Important Note: AIN1 pins also function as Port 1 I/O pins, and must be configured as analog inputs when used as
ADC1 inputs. To configure an AIN1 pin for analog input, set to ‘0’ the corresponding bit in register P1MDIN. Port 1
pins selected as analog inputs are skipped by the Digital I/O Crossbar. See
as Analog Inputs (AIN1.[7:0])” on page 165
AIN1.0 (P1.0)
AIN1.1 (P1.1)
AIN1.2 (P1.2)
AIN1.3 (P1.3)
AIN1.4 (P1.4)
AIN1.5 (P1.5)
AIN1.6 (P1.6)
AIN1.7 (P1.7)
ADC1 (8-BIT ADC)
Analog Multiplexer and PGA
Section “10. VOLTAGE REFERENCE (C8051F021/3)” on page 93
Figure 7.1. ADC1 Functional Block Diagram
AMUX
8-to-1
AMX1SL
Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91
X
for more information on configuring the AIN1 pins.
+
-
AV+
AD1EN
AGND
ADC1CF
Rev. 1.4
ADC
8-Bit
SAR
AV+
ADC1CN
Section “17.1.6. Configuring Port 1 Pins
Start Conversion
C8051F020/1/2/3
8
000
001
010
011
1xx
for C8051F021/3
Write to AD1BUSY
Timer 3 Overflow
CNVSTR
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
75
for

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