EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 174

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

6
VICxIntEnClear
VICxSoftInt
6-12
Vectored Interrupt Controller
EP93xx User’s Guide
31
15
31
15
Definition:
Bit Descriptions:
Address:
Default: Don’t Care
Definition:
Bit Descriptions:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
Interrupt Enable Register. The VICxIntEnable register enables the interrupt
requests by unmasking the interrupt sources. On reset, all interrupts are
disabled (masked).
IntEnable:
VIC1IntEnClear: 0x800B_0014 - Write Only
VIC2IntEnClear: 0x800C_0014 - Write Only
Interrupt Enable Clear Register. The VICxIntEnClear register clears bits in the
VICxIntEnable register.
VIC1SoftInt: 0x800B_0018 - Read/Write
VIC2SoftInt: 0x800C_0018 - Read/Write
IntEnable Clear:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Enables the interrupt request lines:
1 - Interrupt enabled. Allows interrupt request to ARM
Core.
0 - Interrupt disabled.
Clears bits in the VICxIntEnable register. Writing a bit to
“1” clears the corresponding bit in the VICxIntEnable
register. Any bits written to “0” have no effect.
IntEnable Clear
IntEnable Clear
24
24
8
8
SoftInt
SoftInt
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0