EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 361
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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DS785UM1
MOIE:
TxCOIE:
RxROIE:
MIIIE:
PHYSIE:
TIE:
SWIE:
TSQIE:
REOFIE, REOBIE, RHDRIE: Setting all three bits causes interrupts to be
Copyright 2007 Cirrus Logic
Receive Miss Overflow Interrupt Enable. If received
frames are lost due to slow movement of receive data out
of the receive buffers, then a receive miss is said to have
occurred. When this happens, the RxMISS counter is
incremented. When the MSB of the count is set, the
MissCnt bit in the Interrupt Status Register is set. If the
MissCntiE bit is set at this time, an interrupt is generated.
Transmit Collision Overflow Interrupt Enable. When a
transmit collision occurs, the transmit collision count is
incremented. When the MSB of the count is set, the
TXCollCnt bit in the Interrupt Status Register is set. If the
TxCollCntiE is set at this time, an interrupt is generated.
Receive Runt Overflow Interrupt Enable. When a runt
frame is received with a CRC error, the RxRuntCnt register
is incremented. When the MSB of the count is set the
RuntOv bit is set in the Interrupt Status Register. If the
RuntOviE bit is set at this time, an interrupt is generated.
MII Management Interrupt Enable. When set, the MII
Interrupt enable causes an interrupt to be generated
whenever a management read or write cycle is completed
on the MII bus.
The PHY Status Interrupt Enable bit provides a
mechanism to generate an interrupt whenever a change of
status is detected in the PHY.
Setting the Timer Interrupt Enable bit will cause an
interrupt to be generated whenever the general timer (GT)
counter reaches zero.
Writing a “1” to this bit causes a software generated
interrupt to be generated. The SWint bit in the Interrupt
Status register is set to indicate the cause of the interrupt.
This bit will always read zero.
Transmit Status Queue Interrupt Enable. Setting this bit
causes an interrupt to be generated whenever a transmit
status is posted to the transmit status queue.
generated whenever a receive-end-of-frame
status, or a receive-end-of-buffer status, or a
receive-header status is written to the receive
status queue.
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-59
9
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