EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 420

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

10
STATUS
10-26
DMA Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
RSVD
29
13
28
12
Channel Base Address + 0x000C - Read Only
This is the channel status register, which is a read-only register, used to
provide status information with respect to the DMA channel.
RSVD:
Stall:
NFB:
ChError:
BYTES:
27
11
26
10
Copyright 2007 Cirrus Logic
BYTES
25
9
Reserved. Unknown During Read.
A “1” indicates channel is stalled and cannot currently
transfer data because a base address has not been
programmed. When the channel is first enabled, the Stall
bit is suppressed until the first buffer has been transferred,
that is, no stall interrupt generated when STALL state
entered from IDLE state, only when entered from ON
State. The STALL state can be cleared by writing a base
address or disabling the DMA channel. The reason for
channel completion can be ascertained by reading the
BYTES_REMAINING register, if it is zero, the channel was
stopped by the DMA Channel; if it is non-zero, the
peripheral ended transfer with TxEnd/RxEnd. If the
transfer ended with error, ChError bit/interrupt is set.
A “1” indicates the Channel FSM has moved from NEXT
State to ON State. This means that the channel is currently
transferring data from a DMA buffer but the next base
address for the next buffer in the transfer has not been
programmed, and may now be.
0 - Not in ON State, not ready for next buffer update.
1 - In ON State, ready for next buffer BASE/MAXCOUNT
updates. NFB interrupt generated if not masked.
Indicates error status of buffer transfer:
0 - The last buffer transfer completed without error.
1 - The last buffer transfer terminated with an error.
This is the number of valid DMA data currently stored by
the channel in the DMA Controller in packer or unpacker.
Usually used for test/debug.
24
8
RSVD
23
7
NextBuffer
22
6
Current State
21
5
20
4
ChError
19
3
RSVD
18
2
NFB
17
1
DS785UM1
STALL
16
0