EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 76
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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3
3-6
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.1.6 Comparisons
72 bits wide. If the accumulator saturation mode is disabled (the default), the accumulator bit
fields are assigned as below for a 2’s complement integer.
If the saturation mode 1.63 is selected, the bit field assignments are:
If the saturation mode 1.31 is selected, the bit field assignments are:
If the saturation mode 2.62 is selected, the bit field assignments are:
The Crunch co-processor provides four compare operations:
The DSPSC register bit UINT affects the operation of integer comparisons. If clear, integers
are treated as signed values, and if set, they are treated as unsigned. DSPSC.UINT has no
effect on floating point comparisons.
All compare operations update both the FCC[1:0] bits in the DSPSC register and an ARM
register. Though any of the ARM general purpose registers r0 through r14 may be specified
as the destination, specifying r15 actually updates the CPSR flag bits NZCV. This permits the
• CFCMP32 - 32-bit integer
• CFCMP64 - 64-bit integer
• CFCMPS - single floating point
• CFCMPD - double floating point
Opcode
Opcode
Opcode
Opcode
Sign Extension Sign
Sign Extension Sign
71
Sign
71
71
71
Sign Extension
70
64
64
63
63
63
Sign
Copyright 2007 Cirrus Logic
62
62
62
61
Data
Data
32 31
Data
Data
Unused
DS785UM1
0
0
0
0
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