EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 557
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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Part Number
Manufacturer
Quantity
Price
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DS785UM1
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TFS:
Copyright 2007 Cirrus Logic
Receive FIFO Service request. (Read Only)
This bit is a copy of the RIS bit in the UART interrupt
identification register.
0 - RX FIFO is empty or RX is disabled.
1 - RX FIFO not empty and RX enabled.
May generate an interrupt and signal a DMA service
request.
Transmitted Frame Aborted. (Read/Write)
Set “1” when a transmitted frame is terminated with an
abort. Cleared by writing to a “1” to this bit.
Transmit Frame Complete. (Read/Write)
Set to “1” whenever a transmitted frame completes,
whether terminated normally or aborted. Cleared by
writing to a “1” to this bit.
Transmit FIFO Service request. (Read Only)
This bit is a copy of the TIS bit in the UART interrupt
identification register.
0 - TX FIFO is full or TX disabled.
1 - TX FIFO not full and TX enabled. May generate an
interrupt and signal a DMA service request.
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14-35
14
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