EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 724

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

23
Respect to SCLKIN in Microwire Mode
23-12
Synchronous Serial Port
EP93xx User’s Guide
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
SSPRXD
SSPTXD
SFRM
SCLK
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge
of SCLKIN after SFRMIN has gone LOW. Masters that drive a free-running SCLKIN must
ensure that the SFRMIN signal has sufficient setup and hold margins with respect to the
rising edge of SCLKIN.
Figure 23-11
rising edge on which the first bit of receive data is to be sampled by the SSP slave, SFRMIN
must have a setup of at least two times the period of SCLKIN on which the SSP operates.
With respect to the SCLKIN rising edge previous to this edge, SFRMIN must have a hold of
at least one SCLKIN period.
S S P R X D
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements
S F R M IN
S C L K IN
LSB
illustrates these setup and hold time requirements. With respect to the SCLKIN
0
Figure 23-10. Microwire Frame Format (Continuous Transfers)
MSB
4 to 16 bits output data
t
clkm ax
Copyright 2007 Cirrus Logic
t
h o ld
= t
0
S S P C L K IN
LSB
MSB
sam p led b y S S P slave
F irst R X d ata b it to b e
M S B
8-bit control
t
setup
= (2t
S S P C L K IN
)
LSB
MSB
DS785UM1