EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 517
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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BootSts
DS785UM1
31
15
Definition:
Bit Descriptions:
Address: 0x8006_000C - Read Only
Default: 0x0000_0000
Definition:
Bit Descriptions:
30
14
29
13
28
12
The Refresh Timer register is used to specify the period between refresh
cycles.
RSVD:
Refcnt:
When power on reset is asserted, the values of the boot mode option pins
shown in
latched values. This register can be read to determine which memory
configuration was used during the boot process.
RSVD:
ASDO:
Width:
27
11
Table 13-1
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Reserved. - Unknown During Read
Refresh Count - Read/Write
The value written to this field specifies, in multiples of the
period of HCLK, the time period between refresh cycles.
For example, if the period of HCLK is 20 ns, this field
should be written to 0x320 (decimal 800) to generate a
16 ms refresh period. On reset, this field defaults to
0x0080 (decimal 128) to generate a 2.56 ms refresh
period, but it must be written during the SDRAM
initialization routine to the appropriate value for the
SDRAM devices. If this field is written to 0x0000, no
refresh cycles are issued.
Reserved - Unknown During Read
Latched ASDO pin value - Read Only
Boot Media:
1 - SyncROM or SyncFLASH
0 - Asynchronous ROM
Boot memory bus Width - Read Only
are latched. The Boot Status register reflects those
24
8
RSVD
23
7
22
6
SDRAM, SyncROM, and SyncFLASH Controller
21
5
20
4
19
3
Latched
EP93xx User’s Guide
ASDO
18
2
17
1
Width
13-21
16
0
13
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