EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 233

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

VideoAttribs
DS785UM1
INT
31
15
Address: 0x8003_0024
Default: 0x0000_0000
Definition: Video Signal Attributes register.
Bit Descriptions:
INTEN
30
14
PIFEN
29
13
CCIREN
28
12
RSVD:
SDSEL:
BKPXD:
DVERT:
RSVD
RSVD
27
11
LCDEN
26
10
Copyright 2007 Cirrus Logic
ACEN
25
9
Reserved - Unknown during read
SDRAM Selector - Read/Write
Writing to these two bits defines which SDCSn[3:0] pin is
used to access the video frame buffer in SDRAM:
00
01
10
11
SDCSn[3] is selected by default on hardware reset.
Blank Pixel Data - Read/Write
Writing BKPXD = ‘1’ forces the pixel data on the P[17:0]
pins to be 0x0 when the blanking signal on the BLANK pin
is ‘0’.
0 - Disable
1 - Enable
This allows the use of an inexpensive external DAC that
does not contain data blanking logic.
Double Vertical - Read/Write
Writing DVERT = ‘1’ forces the values of the defined bit-
fields in the VLinesTotal, VSyncStrtStop, VActiveStrtStop,
VBlankStrtStop, and
(2X programmed value) when used.
0 - Disable
1 - Enable
Raster Engine With Analog/LCD Integrated Timing and Interface
INVCLK
24
8
SDCSn[3]
SDCSn[0]
SDCSn[1]
SDCSn[2]
BLKPOL
23
7
HSPOL
22
6
SDSEL
VClkStrtStop
V/CPOL
21
5
BKPXD
CSYNC
20
4
registers to be doubled
DVERT
DATEN
19
3
EP93xx User’s Guide
SYNCEN
DHORZ
18
2
EQUSER
PCLKEN
17
1
INTRLC
EN
7-51
16
0
7