EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 262
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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Part Number
Manufacturer
Quantity
Price
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7
HSigStrtStop
7-80
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Bit Descriptions:
Address: 0x8003_020C
Default: 0x0000_0000
Definition: Horizontal Signature Bounds Start/Stop register
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
RSVD:
STOP:
STRT:
RSVD:
STOP:
STRT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VSIGEN signal becomes inactive (stops).This
indicates the end of the signature calculation for the
Vertical frame. VSIGEN is an internal block signal. The
SIG_ENABLE control to the video signature analyzer is
enabled by the logical AND of VSIGEN and HSIGEN.
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VSIGEN signal becomes active (starts).This
indicates the start of the signature calculation for the
Vertical frame. VSIGEN is an internal block signal. The
SIG_ENABLE control to the video signature analyzer is
enabled by the logical AND of VSIGEN and HSIGEN.
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the horizontal down
counter at which the HSIGEN signal becomes inactive
(stops). This indicates the end of the signature calculation
for a horizontal line. HSIGEN is an internal block signal.
The SIG_ENABLE control to the video signature analyzer
is enabled by the logical AND of VSIGEN and HSIGEN.
Start - Read/Write
24
8
23
7
22
6
STOP
STRT
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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