EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 311
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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DS785UM1
9.1.4.6 Hash Filter
The 64 bit Logical Address Filter provides DA filtering hashed by the CRC logic. The Logical
Address Filter is sometimes referred to as the multicast address filter.
Referring to
which is also the first bit of the DA. (Recall that a “frame” is a “packet” without the preamble.)
The CRC Logic can be viewed as a 32 bit shift register with specific Exclusive-OR feedback
taps. After the entire DA has been shifted into the CRC Logic, the signal HashLat latches the
6 most significant bits of the CRC Logic (x
contents of HR are passed through the 6-bit to 64-bit Decoder. Only one of the 64 Decoder
outputs is asserted at a time. That asserted output is compared with a corresponding bit in
the Logical Address Filter. The filter output, Hashed, is used to determine if the received DA
passed the hash filter. When set, the Hashed event bit shows that the received DA passed
the hash filter. When clear, Hashed shows the failure of the DA to pass the hash filter.
Whenever the hashed filter is passed on good frames, the output of the HR is presented on
the Hash Table Index (RStatQ). A received good frame is determined to be one without CRC
error and which is the correct length (64 < length < 1518).
If RXCtl.MA is set, then any received multicast frame passing the hash filter is accepted. A
multicast frame is one which has RXCtl.IA[0] = 1.
If RXCtl.IAHA[0] is set, then a frame with any individual address frame AND passing the hash
filter is accepted. An individual address frame is one which has RXCtl.IA[0] = 0. For a frame
to pass RXCtl.IAHA[0] it must have RXCtl.IA[0] = 0 and pass the hash.
CRC Logic (32 bit shift register with XOR taps)
HashLat
Figure
9-6, notice that the CRC computation starts at the first bit of the frame,
X
26
Hash Register (HR)
Hash Table
6 bit to 64 bit
Decoder
64 bits
6 bits
Copyright 2007 Cirrus Logic
64
Figure 9-6. CRC Logic
X
31
26
through x
6 most significant
bits of the CRC
Hashed
The six HR output lines go to
the Hash Table Index
31
) into the 6-bit hash register (HR). The
1/10/100 Mbps Ethernet LAN Controller
Hashed True = passed filter
Hashed False = failed filter
EP93xx User’s Guide
9-9
9
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