EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 364
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
9
GlIntSts
9-62
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
INT
31
15
Address:
Chip Reset:
Soft Reset:
30
14
29
13
28
12
RxROI:
MIIII:
PHYI:
TI:
AHBE:
OTHER:
TxSQ:
RxSQ:
0x8001_0060 - Read/Write
0x0000_0000
0x0000_0000
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
When a runt frame is received with a CRC error, the
RxRuntCnt register is incremented, when the MSB of the
count is set, the RuntOv bit is set in the Interrupt Status
Register. If the RxROIE bit is set, an interrupt will be
generated.
The MII Status bit is set whenever a management
operation on the MII bus is completed.
The PHY Status bit is set when the MAC detects a change
of status event in the PHY.
The Timeout bit is set when the general timer (GT) count
register reaches zero.
This bit is set if a MAC generated AHB cycle terminated
abnormally. The Queue ID bits (Bus Master Status) will
indicate the DMA Queue which was active when the abort
occurred. DMA operation is halted on all queues until this
bit is cleared, and the queues are restarted via the Bus
Master Control register.
This bit is set when a status other than that covered by bits
10, 3 and 2 is present.
This bit is set when a status affecting the transmit status
queue has been posted.
This bit is set when a status affecting the receive status
queue has been posted. This bit can only be set if bit 2
(REOFIE), bit 1 (REOBIE) and bit 0 (RHDRIE) of the
Interrupt Enable (IntEn) register are set (enabled).
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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