EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 367
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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MII/PHY Access Register Descriptions
MIICmd
DS785UM1
31
15
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
OP
All PHY registers are accessed through the MII Command, Data and Status Registers. Write
operations are accomplished by writing the required data to the MII Data Register and then
writing the required Command to the MII Command Register (Opcode = 01, PhyAd = target
phy, RegAd = target register), which causes the Busy bit (MII Status) to be set. When the
Busy bit is clear, the write operation has been performed. Read operations are performed by
writing a read command to the MII Command register (Opcode = 10b, PhyAd = target phy,
RegAd = source register), which will also cause the Busy bit (MII Status) to be set. When the
read operation has been completed, the Busy bit is cleared and the read data is available in
the MII Data register.
30
14
29
13
28
12
RSVD:
INT:
0x8001_0010 - Read/Write
0x0000_0000
0x0000_0000
MII Command Register. Provides read-write access to the external PHY
registers using the MII command data port.
RSVD:
OP:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Global interrupt force bit, write only, always reads zero.
Writing a one to this bit will set the Global Interrupt Status
bit, if it is enabled. Writing a zero has no effect.
Reserved. Unknown During Read.
OPcode. This Opcode field defines the type of operation to
be performed to the appropriate PHY register.
10 - Read register
01 - Write register
24
8
RSVD
PHYAD
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
REGAD
18
2
17
1
16
9-65
0
9
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