EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 722

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

23
23-10
Synchronous Serial Port
EP93xx User’s Guide
23.5.11 National Semiconductor
SSPR XD
SSPTXD
SFR M
SC LK
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SFRMOUT master signal being driven LOW. The master
SSPTXD output pad is enabled. After a further one half SCLKOUT period, both master and
slave data are enabled onto their respective transmission lines. At the same time, the
SCLKOUT is enabled with a falling edge transition. Data is then captured on the rising edges
and propagated on the falling edges of the SCLKOUT signal.
After all bits have been transferred, in the case of a single word transmission, the SFRMOUT
line is returned to its idle HIGH state one SCLKOUT period after the last bit has been
captured.
For continuous back-to-back transmissions, the SFRMOUT pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state as
described above.
For continuous back-to-back transfers, the SFRMOUT pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
Figure 23-9
frame.
transmitted.
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
t
the SCLKOUT pad (active LOW enable)
the SCLKOUT pad (active LOW enable).
clk_high
Figure 23-10 on page 23-12
M SB
t
clk_low
t
clk_per
shows the National Semiconductor Microwire frame format, again for a single
Figure 23-9. Microwire Frame Format (Single Transfer)
t
clkrf
8-bit control
Copyright 2007 Cirrus Logic
shows the same format when back to back frames are
®
Microwire
L SB
0
M S B
4 to 16 bits output data
™
Frame Format
LSB
DS785UM1