EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 365
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
GlIntMsk
DS785UM1
INT
31
15
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Global Interrupt Status Register
RSVD:
INT:
0x8001_0064 - Read/Write
0x0000_0000
0x0000_0000
Global Interrupt Mask Register. This register is used to mask the GlIntSts bit,
to allow of block interrupts to the processor.
RSVD:
INT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Global interrupt bit. This bit is set whenever the MACint
signal to the interrupt controller is active. Writing a one to
this bit location will clear this bit until a new interrupt
condition occurs.
Reserved. Unknown During Read.
Global interrupt mask bit. When set, any interrupt enabled
by the Interrupt Enable Register will set the Global
Interrupt Status interrupt bit. When clear, no interrupts will
reach the processor.
24
8
RSVD
RSVD
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-63
0
9
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