EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 260
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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7
VidSigCtrl
7-78
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
EN
31
15
Bit Descriptions:
Address: 0x8003_0204
Default: 0x0000_0000
Definition: Video Output Signature Control register
Bit Descriptions:
RSVD
30
14
SPCLK
29
13
BRIGHT
28
12
RSVD:
SIGVAL:
EN:
RSVD:
SPCLK:
BRIGHT:
CLKEN
27
11
BLANK
26
10
Copyright 2007 Cirrus Logic
HSYNC
25
9
Reserved - Unknown during read
Signature Results Value - Read ONly
The Signature Results Value contained in this field is the
16-bit result of the video output signature calculation. This
Signature Results Value is usually updated once per frame
based on the
operation, the Signature Results Value is updated once
every 12 frames.
Enable - Read/Write
Writing a ‘1’ to this bit enables the Linear Feedback Shift
Register (LFSR).
Writing a ‘0’ to this bit disables the LFSR.
Reserved - Unknown during read
Smart Panel/Pixel Clock - Read/Write
Writing a ‘1’ to this bit enables the SPCLK output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the SPCLK output for
calculation in the video signature.
Bright - Read/Write
Writing a ‘1’ to this bit enables the Brightness control
output for calculation in the video signature.
Writing a ‘0’ to this bit disables the Brightness control
output for calculation in the video signature.
VSYNC
24
8
PEN
23
7
SigClrStr
22
6
location. During grayscale
21
5
20
4
PEN
19
3
18
2
17
1
DS785UM1
16
0
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