EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 326
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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Part Number
Manufacturer
Quantity
Price
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9
9-24
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.2.3.5 Receive Descriptor Example
R e ceive D e scrip tor
Q u eu e
Figure 9-11
first frame uses Data buffer 0 only and there are two status entries associated with it. The first
status (status 0) is for the reception of a receive header and the second (status 1) is for the
end of frame/buffer, both status entries point to the beginning of data buffer 0. The second
frame occupies two buffers (data buffers 1 and 2), and three status entries (2, 3, and 4).
Status 2 is for the receive header, status 3 for the end of buffer 1 (frame size larger than
buffer size), and status 4 for end of frame/buffer. The next two frames both occupy one data
buffer each and one status each. This could be the case for short frames that do not exceed
the header size or the buffer size. The result of this is that the status queue may be used at a
different rate to the descriptor queue, based on the type of traffic and the options selected.
R x D e s crip to r 0
R x D e s crip to r 1
R x D e s crip to r 2
R x D e s crip to r 3
R x D e s crip to r 4
R x D e s crip to r 5
R x D e s crip to r 6
R x D e s crip to r 7
shows the state of the receive queues following the reception of four frames. The
Figure 9-11. Receive Descriptor Example
Copyright 2007 Cirrus Logic
Data buffer 0
Data buffer 1
Data buffer 2
Data buffer 3
Data buffer 4
R e ce ive S ta tus
Q ue ue
S tatu s 7
E nd o f fram e &
E nd o f b uffe r
S ta tu s 0
R x H ea d er
S ta tu s 1
E n d o f fra m e &
E n d o f b u ffe r
S ta tus 2
R x H ea d er
Status 3
End of buffer
S ta tu s 4
E n d o f fra m e &
E n d o f b u ffe r
Status 5
End of buffer
S ta tu s 6
E n d o f fra m e &
E n d o f b u ffe r
DS785UM1
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