EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 358
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9
RXRuntCnt
9-56
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Receive Miss Count Register
RSVD:
RMC:
0x8001_0078 - Read Only
0x0000_0000
0x0000_0000
Receive Runt Count Register
RSVD:
RRC:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Miss Count. The Receive Miss Count records the
number of frames that pass the destination address filter,
but fail to be received due to lack of bus availability or lack
of receive storage. Frames that are partially stored and
marked as overruns are included in the count. When the
most significant bit of the count is set, an optional interrupt
may be generated. The register is cleared automatically
following a read, writing to the register will have no effect.
Reserved. Unknown During Read.
Receive Runt Count. The receive runt count records the
total number of runt frames received, including those with
bad CRC. When the most significant bit of the count is set,
an optional interrupt may be generated. The register is
cleared automatically following a read, writing to the
register will have no effect.
24
8
RSVD
RRC
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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