EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 44

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

2
2-6
2.2.3.3.2
2.2.3.3.3
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.2.4 Co-processor Interface
2.2.5 AMBA AHB Bus Interface Overview
The MaverickCrunch co-processor is explained in detail in
relationship between the ARM co-processor instructions and MaverickCrunch co-processor
is also explained in
The ARM co-processor instruction set includes:
The ARM co-processor has sixteen (C0 through C15) 64-bit registers for data transfer and
data manipulation. See
The AHB (Advanced High-Performance Bus) is the high-performance system backbone bus.
Figure 2-2 on page 2-7
The AHB connects devices that require high bandwidth, such as DMA controllers, external
memory, and co-processors. The AHB supports:
The APB (Advanced Peripheral Bus) is a lower bandwidth, but lower power, bus that
provides:
• A write to bit 2 of CP15 register 1 will enable or disable the Data Cache (D-Cache)/Write
• The D-Cache may only be enabled when the MMU is enabled. All data accesses are
• If disabled, current contents are ignored. If re-enabled before a reset, contents will be
• The Write Buffer is enabled via the page table entries in the MMU. The Write buffer
• LDC - Load co-processor from memory
• STC - Store co-processor register from memory
• MRC - Move to ARM register from co-processor register
• MCR - Move to co-processor register from ARM register
• Burst Transactions
• Split Transactions
• Bus Master hand-over to devices such as the MaverickCrunch co-processor or DMA
• Single clock edge operations
Buffer
subject to MMU and permission checks
unchanged, but may not be coherent with external memory. Depending on system
software, a clean and invalidate action may be required before re-enabling.
cannot be enabled unless the MMU is enabled.
controller
Data Cache Enable
Write Buffer Enable
Chapter
shows a typical AMBA AHB System.
Chapter
3.
Copyright 2007 Cirrus Logic
3,
Section 3.2 on page 3-8
Chapter 3 on page
for a code example.
3-1. The
DS785UM1