EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 435
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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- Download datasheet (13Mb)
BCRx
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
BCR0: Channel Base Address + 0x0010 - Read/Write
BCR1: Channel Base Address + 0x0014 - Read/Write
The Channel Bytes Count Register contains the number of bytes yet to be
transferred for a given block of data in a M2M transfer. Only the lower 16 bits
are valid.
RSVD:
BCRx:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
to indicate that the external device has requested service.
The STATUS register is written by software to clear the
DREQS status bit, thus causing the DMA to ignore the
request.
For level-sensitive DREQ mode, do not attempt to clear
the DREQS status bit, as the request will keep coming
from the external device. The hardware ensures that a
write to the STATUS register has no effect when in level-
sensitive mode.
Reserved. Unknown During Read.
x = “0” or “1” representing the double buffer per channel.
The BCR register must be loaded with the number of byte
transfers to occur. It decrements on the successful
completion of the address transfer during the write-to-
memory state of the M2M transfer. At least 1 of the BCRx
registers must be programmed to a non-zero value before
the ENABLE bit and the START bit (in the case of
software-trigger M2M mode) are set in the Control register.
Writing to a BCRx register causes a next buffer update,
that is, only the BCR of the buffer descriptor has to be
written to in order to use that buffer since the SAR_BASEx
and DAR_BASEx registers do not have to be continuously
updated.
24
8
RSVD
BCRx
23
7
22
6
21
5
20
4
19
3
EP93xx User’s Guide
18
2
DMA Controller
17
1
10-41
16
0
10
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