EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 443
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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DS785UM1
11.2.2 Host Controller Interface
11.2.2.1 Communication Channels
There are two communication channels between the Host Controller and the Host Controller
Driver. The first channel uses a set of operational registers located on the HC. The Host
Controller is the target for all communication on this channel. The operational registers
contain control, status, and list pointer registers. Within the operational register set is a
pointer to a location in shared memory named the Host Controller Communications Area
(HCCA). The HCCA is the second communication channel. The Host Controller is the master
for all communication on this channel. The HCCA contains the head pointers to the interrupt
Endpoint Descriptor lists, the head pointer to the done queue, and status information
associated with start-of-frame processing.
Device Enumeration
OpenHCL
Device Register
in memory space
Operational
Mode
HCCA
Status
Event
Frame Int
Ratio
Control
Bulk
Registers
Figure 11-2. Communication Channels
Copyright 2007 Cirrus Logic
Shared RAM
Host Controller
Communications Area
Interrupt 0
Interrupt 1
Interrupt 2
...
Interrupt 31
...
...
Done
Figure 11-2
shows the communication channels.
Universal Serial Bus Host Controller
EP93xx User’s Guide
11-3
11
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