EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 761
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
Available stocks
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Part Number
Manufacturer
Quantity
Price
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DS785UM1
DEVINT:
PINTEN:
PENSTS:
PINT:
NICOR:
TINT:
Copyright 2007 Cirrus Logic
Deviation Interrupt. This is the deviation error interrupt.
When the DINTEN and DTMEN bits are set high and an
axis fails the deviation test 255 times causing an interrupt,
this bit must be written to a “0” to clear the interrupt.
Pen up Interrupt Enable. Setting this bit high causes an
interrupt when the algorithm first detects a pen up
condition.
Pen Status. This bit allows access to directly read the
status of the pen up / down indicator. Read only.
0 - pen up.
1 - pen down.
Pen up Interrupt. This is the Pen up interrupt. When the
PINTEN bit is set and a pen up condition is detected after
a pen down, this bit will be set high and cause the interrupt
output to go high. This bit may be written high for test
purposes and written low to clear the interrupt.
No Interrupt Clear on Read. This bit controls clearing of
the touch interrupt.
0 - TINT clears when reading TSXYResult register.
1 - The TINT bit must be written low to clear the interrupt.
Touch Interrupt. This is the touch screen activation
interrupt. When a new stable set of X and Y ADC values is
resolved, this bit will activate. It may be triggered from an
off-screen unpressed stable value. Writing a “0” to this bit
will clear the touch interrupt. This bit may be written high
for test purposes.
Analog Touch Screen Interface
EP93xx User’s Guide
25-23
25
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