EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 431
![IC ARM9 SOC UNIVERSAL 352PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CBZ
Manufacturer Part Number
EP9312-CBZ
Description
IC ARM9 SOC UNIVERSAL 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1258
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STATUS
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
RSVD
30
14
DREQS
29
13
NB
28
12
Channel Base Address + 0x000C - Read/Write
This is the channel status register, used to provide status information with
respect to the DMA channel. All register bits are read-only except for the
DREQS status bit which can be cleared by a write (either a “0” or a “1”) to this
register.
Write this location once to clear the interrupt (see Interrupt Register Bit
Descriptions for which bits this rule applies to).
RSVD:
Stall:
NFB
27
11
26
10
EOTS
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
A “1” indicates channel is stalled and cannot currently
transfer data because the START bit has not been
programmed or an external device has not asserted
DREQ. When the channel is first enabled, the Stall bit is
suppressed until the first buffer has been transferred, that
is, no stall interrupt generated when STALL state entered
from IDLE state, only when entered from MEM_WR State.
The STALL state can be cleared by:
•Setting the START bit
•An external peripheral requesting service (depending on
•Disabling the DMA channel
•A request from SSP or IDE
transfer mode)
24
8
RSVD
TCS
23
7
DONE
22
6
21
5
20
4
CurrentState
19
3
EP93xx User’s Guide
18
2
DMA Controller
17
1
STALL
10-37
16
0
10
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