EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 731

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
Definition:
Bit Descriptions:
The interrupt status is read from the SSP interrupt identification register
(SSPIIR). A write of any value to the SSP interrupt clear register (SSPICR)
clears the SSP receive FIFO overrun interrupt. Therefore, clearing the RORIE
bit in the SSPCR1 register will also clear the overrun condition if already
asserted. All the bits are cleared to zero when reset.
RSVD:
RORIS:
TIS:
RIS:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Read: SSP Receive FIFO overrun interrupt status
0 - SSPRORINTR is not asserted.
1 - SSPRORINTR is asserted.
This bit is cleared by writing any value to the SSPSR
register
Read: SSP transmit FIFO service request interrupt status
0 - SSPTXINTR is not asserted indicating that the transmit
FIFO is more than half full.
1 - SSPTXINTR is asserted indicating that the transmit
FIFO is less than half full (space available for at least four
half words).
Read: SSP receive FIFO service request interrupt status
0 - SSPRXINTR is not asserted indicating that the receive
FIFO is less than half full.
1 - SSPRXINTR is asserted indicating that the receive
FIFO is more than half full (4 or more half words present in
FIFO)
Synchronous Serial Port
EP93xx User’s Guide
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