R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 165

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324ANSP#U1

Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet

Specifications of R5F21324ANSP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21324ANSP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 135 of 583
Figure 11.8
11.3.10 Interrupt Priority Level Selection Circuit
The interrupt priority level selection circuit is used to select the highest priority interrupt.
Figure 11.8 shows the Interrupt Priority Level Selection Circuit.
Preliminary specification
Specifications in this manual are tentative and subject to change.
Interrupt Priority Level Selection Circuit
Note:
Voltage monitor 1/comparator A1
Voltage monitor 2/comparator A2
Voltage monitor 1/comparator A1
Voltage monitor 2/comparator A2
UART2 bus collision detection
1. Selectable by the IICSEL bit in the SSUIICSR register.
Priority level of interrupts
Oscillation stop detection
UART2 transmit/NACK2
UART2 receive/ACK2
Flash memory ready
UART0 transmit
SSU / I
Watchdog timer
UART0 receive
A/D conversion
Address match
Timer RB
Timer RA
Timer RC
Timer RE
Key input
INT3
INT0
INT1
I flag
IPL
2
C bus
Nov 05, 2008
(1)
Level 0 (initial value)
Highest
Lowest
Peripheral function interrupt priority
(if the priority levels are same)
Interrupt request level
selection output signal
Interrupt request
acknowledgement
11. Interrupts

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