R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 461

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 431 of 583
26.4
Figure 26.2
26.4.1
TRAIC register
LINST register
Figure 26.2 shows an Operating Example during Header Field Transmission in master mode. Figures 26.3 and
26.4 show Examples of Header Field Transmission Flowchart.
During header field transmission, the hardware LIN operates as follows:
(1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a “L” level is output from the
(2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is
(3) The hardware LIN transmits “55h” via UART0.
(4) After the hardware LIN completes transmitting “55h”, it transmits an ID field via UART0.
(5) After the hardware LIN completes transmitting the ID field, it performs communication for a response
SBDCT flag in
Function Description
TXD0 pin for the period set in registers TRAPRE and TRA for timer RA.
set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
field.
TXD0 pin
IR bit in
Master Mode
Preliminary specification
Specifications in this manual are tentative and subject to change.
Operating Example during Header Field Transmission
1
0
1
0
1
0
The above applies when:
LINE = 1, MST = 1, SBIE = 1
Nov 05, 2008
(1)
Synch Break
(2)
(3)
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B1CLR bit in LINST register.
Synch Field
(4)
IDENTIFIER
26. Hardware LIN
(5)