R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 197

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 167 of 583
15.2.1
Notes:
15.2.2
Note:
1. This bit is valid when the MODE bit is 1 (repeat mode).
2. Settings of bits SAMOD and DAMOD are invalid for the repeat area.
3. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
1. When the DTBLS register is set to 00h, the block size is 256 bytes.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b7 to b0
Address See Table 15.4 Control Data Allocation Addresses.
Address See Table 15.4 Control Data Allocation Addresses.
Symbol
Symbol
Bit
RPTSEL Repeat area select bit
DAMOD Destination address control bit
SAMOD Source address control bit
RPTINT Repeat mode interrupt enable bit
Symbol
MODE
CHNE
Bit
Bit
DTC Control Register j (DTCCRj) (j = 0 to 23)
DTC Block Size Register j (DTBLSj) (j = 0 to 23)
—
—
These bits specify the size of the data block to be transferred by one
activation.
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
b7
—
—
X
X
Transfer mode select bit
Chain transfer enable bit
Reserved bits
b6
b6
—
—
X
X
Nov 05, 2008
Bit Name
RPTINT
b5
b5
—
X
X
(1)
(3)
(2)
CHNE
Function
b4
b4
—
X
X
(2)
(1)
DAMOD SAMOD RPTSEL
0: Normal mode
1: Repeat mode
0: Transfer destination is the repeat area.
1: Transfer source is the repeat area.
0: Fixed
1: Incremented
0: Fixed
1: Incremented
0: Chain transfers disabled
1: Chain transfers enabled
0: Interrupt generation disabled
1: Interrupt generation enabled
Set to 0.
b3
b3
—
X
X
b2
b2
—
X
X
Function
b1
b1
—
X
X
MODE
b0
X
b0
—
Setting Range
00h to FFh
X
(1)
15. DTC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W