R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 332

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 302 of 583
Figure 21.3
• Transmit Timing Example (Internal Clock Selected)
• Receive Timing Example (External Clock Selected)
S0TIC register
U0C1 register
U0C0 register
U0C1 register
S0RIC register
U0C1 register
U0C1 register
U0C1 register
U0C1 register
Transfer clock
TXEPT bit in
RE bit in
TE bit in
TE bit in
IR bit in
The above applies when:
RI bit in
TI bit in
TI bit in
IR bit in
The above applies when:
The following should be met when “H” is applied to the CLK0 pin before receiving data:
TXD0
CLK0
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
• U0IRS bit in U0C1 register = 0
CLK0
RXD0
fEXT: Frequency of external clock
receive data input at the rising edge of the transfer clock)
(interrupt request generation when the transmit buffer is empty)
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
• TE bit in U0C1 register = 1 (transmission enabled)
• RE bit in U0C1 register = 1 (reception enabled)
• Dummy data is written to U0TB register
receive data input at the rising edge of the transfer clock)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in U0TB register.
Dummy data is set in U0TB register.
Data transfer from UART0 receive register
Data transfer from U0TB register to UART0 transmit register
Data transfer from U0TB register to UART0 transmit register
D0
D0
D1
D1
D2
D2
TCLK
Nov 05, 2008
D3
D3
to U0RB register
1/fEXT
D4
D4
TC
Receive data taken in
D5
D5
D6
D6
Set to 0 by an interrupt request acknowledgement or by a program.
D7
D7
D0 D1
D0 D1
Set to 0 when an interrupt request is acknowledged or by a program.
D2
D3
D2
Data read from U0RB register
D3
D4
D5
D4
D6
D5
TC = TCLK = 2(n+1)/fi
D7
fi: Frequency of U0BRG count source (f1, f8, f32, fC)
n: Setting value in U0BRG register
Pulsing stops because TE bit is set to 0.
D0 D1
21. Serial Interface (UART0)
D2
D3
D4
D5
D6
D7