R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 360

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 330 of 583
Figure 22.5
22.3.3
22.3.4
Use the UFORM bit in the U2C0 register to select the transfer format. Figure 22.5 shows the Transfer Format.
In continuous receive mode, receive operation is enabled when the receive buffer register is read. It is not
necessary to write dummy data to the transmit buffer register to enable receive operation in this mode.
However, a dummy read of the receive buffer register is required when starting the operating mode.
When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register
is set to 0 (data present in the U2TB register) by reading the U2RB register. If the U2RRM bit is set to 1, do not
write dummy data to the U2TB register by a program.
LSB First/MSB First Select Function
Continuous Receive Mode
(1) UFORM Bit in U2C0 Register = 0 (LSB first)
(2) UFORM Bit in U2C0 Register = 1 (MSB first)
The above applies when:
Preliminary specification
Specifications in this manual are tentative and subject to change.
Transfer Format
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
•
•
CKPOL bit in U2C0 register = 0
(transmit data output at the falling edge and receive data input
U2LCH bit in U2C1 register = 0 (not inverted)
at the rising edge of the transfer clock)
Nov 05, 2008
D7
D0
D0
D7
D6
D1
D1
D6
D5
D2
D2
D5
D4
D3
D3
D4
D3
D4
D3
D4
D2
D5
D5
D2
D6
D6
D1
D1
D7
D7
D0
D0
22. Serial Interface (UART2)