R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 457

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 427 of 583
26. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
26.1
Figure 26.1
RXD0 pin
TXD0 pin
The hardware LIN has the features listed below.
Figure 26.1 shows a Hardware LIN Block Diagram.
Master mode
•
•
Slave mode
•
•
•
•
Synch Break generation
Bus collision detection
Synch Break detection
Synch Field measurement
Control function for Synch Break and Synch Field signal inputs to UART0
Bus collision detection
Overview
Note:
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
1.The Wake up function is detected using INT1.
LSTART bit
Hardware LIN
Preliminary specification
Specifications in this manual are tentative and subject to change.
Hardware LIN Block Diagram
LINE bit
SBE bit
RXD0 input
Nov 05, 2008
control
circuit
Synch Field
control
circuit
TIOSEL = 0
TIOSEL = 1
Bus collision
detection
circuit
MST bit
Bits BCIE, SBIE,
RXD data
and SFIE
Interrupt
control
circuit
Timer RA output pulse
UART0 transfer clock
UART0 TXD data
UART0 TE bit
underflow signal
Timer RA
Timer RA
UART0
26. Hardware LIN
Timer RA
interrupt