R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 20

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.
27.
25.3
25.4
25.5
25.6
25.7
25.8
25.9
26.1
26.2
26.3
26.4
26.5
26.6
27.1
27.2
25.2.2
25.2.3
25.2.4
25.2.5
25.2.6
25.2.7
25.2.8
25.2.9
25.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 400
25.2.11 Slave Address Register (SAR) .......................................................................................................... 401
25.2.12 IIC bus Shift Register (ICDRS) ........................................................................................................ 401
25.3.1
25.3.2
25.3.3
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.5.1
25.5.2
25.5.3
26.3.1
26.3.2
26.3.3
26.4.1
26.4.2
26.4.3
26.4.4
27.2.1
Hardware LIN .............................................................................................................................. 427
A/D Converter ............................................................................................................................. 442
Common Items for Multiple Modes ...................................................................................................... 402
I
Clock Synchronous Serial Mode ........................................................................................................... 417
Examples of Register Setting ................................................................................................................ 420
Noise Canceller ..................................................................................................................................... 424
Bit Synchronization Circuit ................................................................................................................... 425
Notes on I
Overview ............................................................................................................................................... 427
Input/Output Pins .................................................................................................................................. 428
Registers ................................................................................................................................................ 429
Function Description ............................................................................................................................. 431
Interrupt Requests .................................................................................................................................. 440
Notes on Hardware LIN ........................................................................................................................ 441
Overview ............................................................................................................................................... 442
Registers ................................................................................................................................................ 444
2
C bus Interface Mode ......................................................................................................................... 406
SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 393
I/O Function Pin Select Register (PINSR) ....................................................................................... 394
IIC bus Transmit Data Register (ICDRT) ......................................................................................... 395
IIC bus Receive Data Register (ICDRR) .......................................................................................... 395
IIC bus Control Register 1 (ICCR1) ................................................................................................. 396
IIC bus Control Register 2 (ICCR2) ................................................................................................. 397
IIC bus Mode Register (ICMR) ........................................................................................................ 398
IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 399
Transfer Clock .................................................................................................................................. 402
SDA Pin Digital Delay Selection ...................................................................................................... 404
Interrupt Requests ............................................................................................................................. 405
I2C bus Format ................................................................................................................................. 406
Master Transmit Operation ............................................................................................................... 407
Master Receive Operation ................................................................................................................ 409
Slave Transmit Operation ................................................................................................................. 412
Slave Receive Operation ................................................................................................................... 415
Clock Synchronous Serial Format .................................................................................................... 417
Transmit Operation ........................................................................................................................... 418
Receive Operation ............................................................................................................................. 419
LIN Control Register 2 (LINCR2) .................................................................................................... 429
LIN Control Register (LINCR) ......................................................................................................... 430
LIN Status Register (LINST) ............................................................................................................ 430
Master Mode ..................................................................................................................................... 431
Slave Mode ....................................................................................................................................... 434
Bus Collision Detection Function ..................................................................................................... 438
Hardware LIN End Processing ......................................................................................................... 439
On-Chip Reference Voltage Control Register (OCVREFCR) ......................................................... 444
2
C bus Interface .................................................................................................................... 426
A - 11