R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 348

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 318 of 583
22.2.4
Notes:
1. If bits CLK1 to CLK0 are switched, set the U2BRG register again.
2. The UFORM bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00ACh
serial I/O mode), or set to 101b (UART mode, transfer data 8 bits long).
Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I
are set to 100b (UART mode, transfer data 7 bits long) or 110b (UART mode, transfer data 9 bits long).
Symbol UFORM
UFORM Transfer format select bit
Symbol
CKPOL CLK polarity select bit
TXEPT
Bit
CLK0
CLK1
CRD
NCH
CRS
UART2 Transmit/Receive Control Register 0 (U2C0)
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
0
U2BRG count source
select bit
CTS/RTS function select bit
Transmit register empty flag
CTS/RTS disable bit
Data output select bit
CKPOL
b6
(1)
0
Nov 05, 2008
Bit Name
NCH
b5
0
(2)
CRD
b4
0
0: Pins TXD2/SDA2, SCL2 set to CMOS output
b1 b0
Enabled when CRD = 0
0: CTS function selected
1: RTS function selected
0: Data present in the transmit register
1: No data in the transmit register
0: CTS/RTS function enabled
1: CTS/RTS function disabled
1: Pins TXD2/SDA2, SCL2 set to N-channel open-drain
0: Transmit data output at the falling edge and receive
1: Transmit data output at the rising edge and receive
0: LSB first
1: MSB first
0 0: f1 selected
0 1: f8 selected
1 0: f32 selected
1 1: fC selected
(transmission in progress)
(transmission completed)
output
data input at the rising edge of the transfer clock
data input at the falling edge of the transfer clock
TXEPT
b3
1
CRS
b2
0
2
C mode), and to 0 when bits SMD2 to SMD0
Function
CLK1
b1
0
22. Serial Interface (UART2)
CLK0
b0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R