R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 386

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 356 of 583
Figure 22.22
22.6.3
input signal
Sampling
RXD2
clock
When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is
loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded
latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a
frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit
when three latch outputs match. When the outputs do not match, the previous value is retained.
In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise.
Figure 22.22 shows a Block Diagram of RXD2 Digital Filter Circuit.
Note:
RXD2 Digital Filter Select Function
Internal basic clock
1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1)
Sampling clock
D
(fj = f1, f8, f32, fC; n = setting value in the U2BRG register).
When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1)
(fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).
Block Diagram of RXD2 Digital Filter Circuit
Preliminary specification
Specifications in this manual are tentative and subject to change.
period
Latch
C
(1)
Q
Nov 05, 2008
D
Latch
C
Q
D
Latch
C
Q
detection
Match
circuit
(DF2EN bit)
22. Serial Interface (UART2)
URXDF
register
Internal RXD2
input signal