R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 390

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 360 of 583
24. Synchronous Serial Communication Unit (SSU)
Synchronous serial communication unit (SSU) supports clock synchronous serial data communication.
24.1
Table 24.1
Note:
Transfer data format
Operating modes
Master/slave device
I/O pins
Transfer clocks
Receive error detection • Overrun error
Multimaster error
detection
Interrupt requests
Select functions
Table 24.1 lists a Synchronous Serial Communication Unit Specifications, Figure 24.1 shows a Block Diagram of
Synchronous Serial Communication Unit and Table 24.2 lists the Pin Configuration of Synchronous Serial
Communication Unit.
1. Synchronous serial communication unit has only one interrupt vector table.
Overview
Item
Preliminary specification
Specifications in this manual are tentative and subject to change.
Synchronous Serial Communication Unit Specifications
• Transfer data length: 8 to 16 bits
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
• When the MSS bit in the SSCRH register is set to 1 (operates as master
• Clock polarity and phase of SSCK can be selected.
• Conflict error
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error)
• Data transfer direction
• SSCK clock polarity
• SSCK clock phase
device), external clock is selected (input from SSCK pin).
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Selects MSB-first or LSB-first
Selects “L” or “H” level when clock stops
Selects edge of data change and data download
Nov 05, 2008
24. Synchronous Serial Communication Unit (SSU)
(1)
Specification
.