R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 291

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 261 of 583
Figure 19.14
19.6.3
TRCSR register
TRCSR register
TRCSR register
TRCSR register
TRCIOD output
TRCIOB output
TRCIOC output
IMFC bit in
IMFD bit in
IMFA bit in
IMFB bit in
Operating Example
Count source
Value in TRC register
Preliminary specification
Specifications in this manual are tentative and subject to change.
Operating Example of PWM Mode
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• Bits TOB and TOC in the TRCCR1 register are set to 0 (inactive level), the TOD bit is set to 1 (active level).
• The POLB bit in the TRCCR2 register is set to 1 (“H” active), bits POLC and POLD are set to 0 (“L” active).
1
0
1
0
1
0
1
0
m
n
p
q
to compare match
to compare match
Initial output “H”
to compare match
Initial output “L”
Initial output “L”
Nov 05, 2008
Active level “H”
Active level “L”
Set to 0 by a program
Set to 0 by a program
q+1
Inactive level “H”
Inactive level “L”
p+1
n+1
m+1
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
q: TRCGRD register setting value
m-q
Set to 0 by a program
m-p
m-n
Set to 0 by a program
19. Timer RC