R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 358

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 328 of 583
Figure 22.3
S2RIC register
U2C1 register
U2C1 register
(1) Transmit Timing Example (Internal Clock Selected)
(2) Receive Timing Example (External Clock Selected)
U2C1 register
U2RB register
U2C1 register
The above applies when:
The above applies when:
fEXT: Frequency of external clock
Transfer clock
S2TIC register
U2C1 register
U2C1 register
TXEPT flag in
U2C0 register
OER flag in
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
TE bit in
RE bit in
receive data input at the rising edge of the transfer clock)
receive data input at the rising edge of the transfer clock)
RI bit in
TI bit in
IR bit in
TE bit in
RXD2
RTS2
IR bit in
CLK2
TI bit in
CTS2
CLK2
TXD2
“H”
“L”
1
0
1
0
1
0
1
0
1
0
1
0
“H”
“L”
1
0
1
0
1
0
1
0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data transfer from UART2 receive
register to U2RB register
Data is set in U2TB register.
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Dummy data is set in U2TB register.
Data transfer from U2TB register to UART2 transmit register
Nov 05, 2008
Set to 0 when an interrupt request is acknowledged or by a program.
TCLK
1/fEXT
Received data taken in
TC
Data transfer from U2TB register to UART2 transmit register
Data read from U2RB register
Pulsing stops because “H” is applied
to CTS2.
D0 D1 D2 D3 D4 D5
Set to 0 when an interrupt request is acknowledged or by a program.
“L” is applied when U2RB register is read.
D0 D1 D2 D3 D4 D5 D6 D7
D6
D7
Make sure the following conditions are met
when the CLK2 pin input before receiving data is high:
• TE bit in U2C0 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data is written to U2TB register
D0 D1 D2 D3 D4 D5
TC = TCLK = 2(n+1)/fj
Pulsing stops because TE bit is set to 0.
fj: Frequency of U2BRG count source
n: Setting value in U2BRG register
D0 D1 D2 D3 D4 D5 D6 D7
(f1, f8, f32, fC)
22. Serial Interface (UART2)
D6